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The simulation seems to suggest that there is just enough headroom to include series resistors in this branching I2C network

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There is one master and four peripherals, each connected over longish (300mm) tracks; the challenge is to add enough series resistance to smooth out the switching oscillations, while still leaving enough margin between the worst-case input/output voltages of the devices on the network. In reality the parasitic values should be much lower than I have here.

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