The easy part of FPGA projects is wiring them: just plug into whatever pin is convenient! That hard part is actually writing working Verilog that can handle clock domain crossing to external devices.

  • single SPI reads and writes are steered to the correct chip via logic in spi_clk_in domain
  • Reads that span the chip boundaries work fine
  • Writes are not allowed to pass chip boundaries (since they are page aligned)
  • Writes are currently passed through unchanged, which is incorrect for NOR flash, although a buffer is in place to emulate it.
  • No serial communication is in place yet.
  • qspi works in the simulator, need to wire up the direction of the IO pins for quad reads on real hardware.
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