Don't want to spoil the joke thread with a serious response, but -- what processor DOES the JWST use? How out of date is it given the project started in the 90s?
The primary compute bits include the science instrument data handling electronics, the Solid State Recorder (SSR) and the Command & Data Handling processor (C&DH).
NASA has plenty of publications about the design, I haven't found anything yet that covers the SSR or C&DH yet, but this is an interesting article about implementing SpaceWire reliable messaging in an FPGA.
https://ntrs.nasa.gov/api/citations/20030025278/downloads/20030025278.pdf?attachment=true
The science data handling here is done in an Actel AX1000 FPGA.
@th JWST note like JSWT amirite
Running on PowerPC, which answers the original question I think. Foone has the details:
@EdS @th PowerPC is the architecture, doesn't answer what chip it is, probably it's a RAD750 since that's the most common for usgov space designs.
Ah and wikipedia confirms...
https://en.m.wikipedia.org/wiki/RAD750
"James Webb Space Telescope, launched 25 December 2021, uses one RAD750 clocked at 118 MHz."
Foone's speculation of triple redundancy is unlikely, NASA only does that for human life critical systems and it's not mentioned in any of the jwst docs.
@eqe and they can be modifid:
> The fact that the OSS is written in JavaScript and stored on-board as text files is significant because this gives the operations personnel greater visibility, control and flexibility over the telescope operations. As they learn the ramifications and subtleties of operating the instruments, they can modify the JavaScripts and, after thorough testing in a ground facility, they can simply replace an onboard file to make the change.