Don't want to spoil the joke thread with a serious response, but -- what processor DOES the JWST use? How out of date is it given the project started in the 90s?
The primary compute bits include the science instrument data handling electronics, the Solid State Recorder (SSR) and the Command & Data Handling processor (C&DH).
NASA has plenty of publications about the design, I haven't found anything yet that covers the SSR or C&DH yet, but this is an interesting article about implementing SpaceWire reliable messaging in an FPGA.
https://ntrs.nasa.gov/api/citations/20030025278/downloads/20030025278.pdf?attachment=true
The science data handling here is done in an Actel AX1000 FPGA.
@eqe https://jwst.nasa.gov/resources/ISIMmanuscript.pdf has some details, including discussion of Rational Rose Real-Time UML and communication on the Spacewire bus.
