@th tooting my own horn.

My verilog reprocessor tool has a FORINST macro that would be handy in scenarios like this. Nobody but me uses this tool, but I can't live without it.

github.com/jonmayer/verilogpp

@th I know, I need to rewrite it in python or I shall be shunned. Or perhaps leverage the verible parser to rebuild it in C++.

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