How is the Verilog debugging going? Well...
@whitequark if you have to open the place and route gui to figure out why it's not meeting timing, you've already lost.
@th Sorta the equivalent of staring at assembly listings when trying to figure out exactly what did a compiler do to my "simple" code. Of course, in this case, it sometimes is helpful because I suddenly realize how some innocent looking verilog generate statement blew up in some unanticipated way. (Or perhaps my architecture is just bad for what I'm trying to do.)
Anyway, good times.
@th oh no