Trammell Hudson @th@v.st
Today's success: a risc-v softcore running C code, decoding the spispy fpga's control registers to monitor the data on the SPI bus. Works in simulation and on real hardware!
* single SPI reads and writes are steered to the correct chip via logic in spi_clk_in domain
* Reads that span the chip boundaries work fine
* Writes are not allowed to pass chip boundaries (since they are page aligned)
* Writes are currently passed through unchanged, which is incorrect for NOR flash, although a buffer is in place to emulate it.
* No serial communication is in place yet.
* qspi works in the simulator, need to wire up the direction of the IO pins for quad reads on real hardware.
The easy part of FPGA projects is wiring them: just plug into whatever pin is convenient! That hard part is actually writing working Verilog that can handle clock domain crossing to external devices.
Although Amsterdam is only 52°N, the midnight sky is still quite bright during the summer solstice.
Computer dating (1924). https://archive.org/details/ScienceandInvention192404
Computer at work in the engine research building. @retrocopmuting https://archive.org/details/C-1956-42046
Computer at work with her planimeter. #retrocomputing https://archive.org/details/C-1954-35053
Computer at work with her Friden mechanical calculator. #retrocomputing https://archive.org/details/C-1954-35057
