The worlds lowest resolution HDMI display makes for a fine demo, although it is not the most interesting use case for the pixel wrangler.
For a legacy structure like the Intel GDT that has grown over many decades, or for ease of hardware implementation like the RISC-V it makes sense. But for a purely software parsed structure like the HDMI EDID, why would you do this?
Getting quite a bit of ghosting so it probably needs to drive all zeros between scan lines.
This LED matrix is not quite hub75 protocol, although still an easy output for the pixel wrangler.
dear lazyweb: is there a way to ensure that the ice40 PLL output has a consistent phase with the reference clock? it seems to be arbitrary, which causes problems for deserializing a TMDS data stream. my work around makes me feel dirty since it just bangs the reset line until the clocks seem to be in sync.